home   contact   中文   cas
About Us Research People International Cooperation News Education & Training Societies & Publications Papers Resources Links
Location: Home > News > Events
Members of the 11th Laboratory (System on Programmable Chip Research Department) were invited to attend the 25th International Conference on Field Programmable Logic and Applications
Update time: 2015-10-21
Text Size: A A A

The 25th International Conference on Field Programmable Logic and Applications was held in London, England, from August 31st to September 4th, 2015. The Conference was hosted by Imperial College, and organized by the Institute of Electrical and Electronic Engineers (IEEE) and IEEE Circuits and Systems Society (IEEE CAS). The Conference received a total of 240 contributions, including 216 articles, 12 contributions to the Doctoral Forum, and 12 presentations. After being reviewed by the technical committee, 48 contributions were accepted as presentations (with an acceptance ratio of 22.2%), and 41 were accepted as posters (acceptance ratio of 17.1%)

The article entitled A Technology Mapper for Depth-Constrained FPGA Logic Cells, collaboratively authored by System on Programmable Chip Research Department, Institute of Electronics, and the Laboratory of Processor Architecture, École Polytechnique Federale de Lausanne, was accepted by the organizers of the Conference. This article is one of several articles whose full texts were indexed by the Conference in mainland China, and the only one accepted on the special topic of Design Philosophy and Tools. Our laboratory has signed an agreement with École Polytechnique Federale de Lausanne for the development of novel programmable logic chips. This win-win collaboration can attain the aim of mutual advantages. The article also marks a significant phased breakthrough of the combination.

This paper pointed out that the advancement in logic synthetic tools has brought about a circuit expression which is closer to Boolean algebra, analyzed the shortcomings and deficiencies of the traditional mapping tools based on LUT structure in dealing with the novel logic units, and developed a set of general mapping tools with preferable flexibility and stronger applicability. The developed mapping tool adopts a forward search mode, and is characterized by adjustable input and output parameters, as well as mapping depth and alternative mapping schemes. Compared with traditional open-source tools, this mapping tool was improved in terms of the area and key path of mapping , which can provide effective means for exploring and developing more advanced logical units and structures. [NA1]Right?

<< >>
Copyright © 2002 - 2009 Institute Of Electronics Chinese Academy Of Scences Email: iecas@mail.ie.ac.cn