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New Progress in the Design of Low-Noise Amplifier
Update time: 2015-07-10
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Structural diagram of low-noise instrumentation amplifier


   The IEEE ISCAS 2015 (IEEE International Symposium on Circuits and Systems) was held from 24 to 27 May in Lisbon, Portugal. Nearly 1000 experts and scholars from around the world attended the symposium. IEEE ISCAS, as an important conference in the field of international circuits and systems, has been held every year since 1967, and is widely regarded by both academic and industrial circles. The thesis “A 1.3 μW 0.7μ VRMS Chopper Current-Reuse Instrumentation Amplifier for EEG Applications”, presented by the team of the Programmable Chip and System Laboratory, was included as an oral report at IEEE ISCAS 2015. Yang Haigang and Yin Tao attended the conference as representatives.

  For the application requirements of low noise, low power consumption, high input impedance and high CMRR (Common Mode Rejection Ratio) in EEG detection, the thesis details an advanced [NA1] low-noise instrumentation amplifier which is able to automatically eliminate its offset voltage by means of chopper technology and current-reuse technology. The thesis also describes a Ripple Reduction Loop (RRL) based on output resistance adjustment, which eliminates the output voltage fluctuation caused by maladjustment, and adopts a Positive Feedback Loop (PFL) to enhance the input impedance of circuits. The amplifier consumes a current of only 1.2 μA when working at a low supply voltage of 1-1.8 V, its equivalent input noise is 0.7 μV within EEG bandwidth range, and it has CMRR and PSRR (Power Supply Rejection Ratio) above 100 dB, as well as a high input impedance of 1.5 Gohm. Moreover, this amplifier has important application value in EEG detection and other forms of bio-medical treatment. (Room 11, Yin Tao)



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